1. Field of the Invention
The present invention relates to analog-to-digital conversion, and more particularly to performing analog-to-digital conversion without requiring a clock signal.
2. Description of the Prior Art
The front-end portion of a radiation detection system, as shown in FIG. 1, typically includes a sensor 12 (e.g. pixel), which provides the conversion of the ionizing radiation into a charge Q, a charge amplifier 14, which provides conversion of the charge Q into a voltage V, and a filter or shaping amplifier 16, which shapes the signal into a pulse P shown in FIG. 2 with an amplitude proportional to the charge Q. The sensor 12 has pixel capacitance Cp, the charge amplifier 14 has input capacitance Ci and feedback capacitance Cf, and the filter 16 has a shaped pulse peaking time τP.
Due to its proportionality to the input charge Q, the peak amplitude of the shaped pulse P is the quantity of interest and it is subject to further signal processing. In all cases, the peak amplitude is converted (quantized) into one of m discrete levels. In some applications, a counter is associated with each of the m levels, and the counter is incremented if the amplitude of an event falls within that level. In other applications, an encoded digital word (typically an n-bit word where m=2n) is associated with each of the m levels, and for each event a corresponding digital word is stored. Depending on the application, the number m of discrete levels can vary from the simplest case of 1, where if the amplitude is below threshold, the bit is 0, and if the amplitude is above threshold, the bit is 1, to a number that can be as high as 20 or more for very high resolution measurements.
The need for high spatial resolution and high rate capability requires the development of radiation detection systems in which the front-end and processing electronics per channel is highly integrated. Application Specific Integrated Circuits (ASICs) that integrate an increasing amount of front-end and processing electronics are needed in order to satisfy these requirements. The integration of efficient circuits for the processing of the shaped pulses represents a challenge, especially when the number m of discrete levels exceeds a few units.
Previous attempts to solve this problem of processing the shaped pulses include: (a) multiple windows discrimination, (b) analog peak detection followed by peak digitization, and (c) shaped pulse digitization with digital peak detection. These concepts, their disadvantages, and their shortcomings are discussed below.
Multiple-Windows Discrimination
When the number of discrete levels m is limited to a few units, the multiple-windows discrimination approach is typically adopted, as shown in FIG. 3. This approach uses m−1 discriminators 18 (each referenced to a defined threshold level) and additional logic 20 in order to select the appropriate window in correspondence to the event. Some applications may require the use of only two windows realized by a single threshold level, thus simply identifying the occurrence of the event. Other applications may need more windows in order to provide the required amplitude discrimination.
The main disadvantage of this approach appears when the number of windows exceeds a few units. The power dissipated by each discriminator 18, depending on the required speed and accuracy, ranges typically around several tens of μW or more. Since the power dissipated by the whole front-end channel must frequently be contained within a few hundreds of μW or less, only a very limited number of discriminators 18, and consequently discrete levels, can be implemented in a single channel.
Analog Peak Detection Followed by Peak Digitization
As the number of discrete levels m increases above a few units, the multiple-windows discrimination approach becomes impractical and the analog peak detection with peak digitization method shown in FIG. 4 is typically adopted. This approach uses a peak detection circuit 22 followed by an n-bit analog-to-digital converter (ADC) 24, thus providing m=2n windows. The accuracy required from the peak detection circuit 22 to the ADC 24 (i.e. number n of bits) depends on the application.
The primary disadvantage of this approach is the amount of power required by the peak detection and the on-chip analog-to-digital conversion per channel. The peak detection circuit 22 may dissipate only a few hundreds of μWs. But the typical power dissipation of the ADC 24 can be very high, depending on the required speed (samples per second, S/s) and resolution (i.e. number n of bits). There are a very large number of ADC architectures available, but only very few configurations may actually satisfy the stringent power requirements of any particular application. Some mixed solutions make use of multiplexers and arbitration logic to share one ADC among several channels to save power, but this saving is at the expense of substantially greater complexity.
Another disadvantage of this approach is the need for an external or internally generated clock signal, which is required by the ADC 24 in order to provide the conversion. The clock signal can easily interfere with the low-noise analog front-end circuitry with consequent degradation of the resolution. The clock frequency depends on the speed of the ADC 24, and the number of clock cycles per conversion can be as high as n for a low-power ADC.
One last disadvantage is represented by the total amount of time required for detecting and converting the peak, which is equal to the sum of the peak detection time plus the conversion time. Depending on the speed of the ADC and the rate of the application, this time can become long enough to cause loss of data.
Shaped Pulse Digitization with Digital Peak Detection
The shaped pulse digitization with digital peak detection approach shown in FIG. 5 uses a fast n-bit ADC 26 to convert the shaped pulse before a digital peak detection circuit 28. The peak is digitally extracted by the peak detection circuit 28 using a Digital Signal Processor (DSP). The accuracy and speed required from the ADC depend on the application.
The main disadvantage of this approach is the power required to provide fast on-chip analog-to-digital conversion per channel. The power dissipation of the fast ADC 26 can be very high (and will likely exceed that of the analog peak detection followed by peak digitization approach described above) depending on the required speed and resolution. In addition, the disadvantage of requiring an external or internally generated clock applies in this method.
Thus, there is need in radiation detection systems for peak detection and analog-to-digital conversion of the shaped analog pulse, which represents an ionizing event, which minimizes power requirements and does not require a clock signal.